1. Field of the Invention
This invention relates generally to a non-volatile semiconductor memory device. In particular, this invention relates to a non-volatile semiconductor memory cell having a control gate and a floating gate in a stacked arrangement and capable of storing data of three different levels, and to a non-volatile semiconductor memory device incorporating the memory cells of the type described.
2. Description of the Background Art
Memory devices for non-volatile storage of information are widely used in diverse applications in diverse fields of technology. One of the non-volatile memory device is the electrically programmable read only memory or EPROM. The operation and electrical characteristics of the EPROM are reviewed in an article by D. Knowlton entitled "Versatile Algorithm, Equipment Cut EPROM Programming Time" (EDN, Mar. 17, 1983 or Intel Corp. Article Reprint AR-265, pp. 4-119 to 4-122) and in an article by J. Barns et al entitled "Operation and Characterization of N-channel EPROM Cell" (Solid State Electronics, Vol. 21, 1978, pp. 521-529).
Now, description is made briefly of a double-gate EPROM cell in its structure and operation. With reference to FIG. 1, the double-gate EPROM cell is formed on a P.sup.- type semiconductor substrate 1. N-type impurities are ion-implanted into a predetermined region of the substrate 1 to form an impurity region 2 which serves as a drain region. Another impurity region 3 is likewise formed in the semiconductor substrate 1 spaced away from the drain impurity region 2, and acts as a source region. An electrically conductive floating gate 4 made, for example, of polysilicon is disposed over the area of the substrate surface between the drain region 2 and the source region 3 with an insulation film 5 interposed between the floating gate and the substrate surface. Overlying the floating gate 4 is formed a control gate 6 with an insulation layer 7 interposed therebetween.
The floating gate 4 is formed to overlap at its opposite ends the drain impurity region 2 and the source impurity region 3 in a planar view.
In a memory cell array where a plurality of the double-gate memory cells of the type described above are arranged in a matrix of rows and columns, the control gate 6 of each memory cell is connected to a word line for selecting a row, while the drain impurity region 2 is coupled to a bit line for selection of a column. Then, the operation of the memory device will be described.
An injection of electrons into the floating gate of the memory cell in a programming mode is first explained. In the programming mode, the control gate 6 is supplied with a high potential of about 12.5 V, and the drain impurity region 2 is supplied with a high level potential of about 8 V, with both the semiconductor substrate 1 and the source impurity regions 3 grounded. Under the condition, the double-gate MOS transistor forming the memory cell operates in the saturation region. However, the application of the high level potential in the order of 8 V to the drain impurity region 2 causes the inversion region that has been created in the substrate under the floating gate 4 to be pinched off at a portion near the drain region 2. In the pinched-off region between the channel region (or the inversion region) and the drain impurity region 2, electrons are accelerated by the drain-to-source voltage with a constant saturation voltage applied across the channel region. Then, a high intensity electric field is induced in the pinched-off region near the drain region 2. The high intensity electric field accelerates electrons from the channel region into hot electrons which in turn jump over the potential barrier of the gate insulation layer 5 into its conduction band. The hot electrons in the conduction band of the insulation layer 5 are then attracted to and trapped into the floating gate 4 by the effect of the high positive potential level at which the floating gate is maintained. Consequently, the electrons are injected into the floating gate 4, resulting in non-volatile data writing. The voltage Vfg applied to the floating gate 4 is expressed as follows: EQU Vfg=V.sub.G .multidot.C1/(C1+C2),
where V.sub.G is the gate voltage applied to the control gate 6; C1 represents a capacitance provided by the control gate 6, the interlayer insulating layer 7 and the floating gate 4; and C2 represents a capacitance by the floating gate 4, the gate insulation film 5 and the semiconductor substrate 1.
With injection of the electrons into the floating gate 4, the MOS memory cell transistor shifts its threshold voltage in a positive direction.
To erase the data stored in the memory cell, the double-gate MOS transistor is exposed to ultra-violet (UV) light. Under illumination of UV light, the electrons trapped in the floating gate 4 are excited to such a level that they move across the potential barriers of the gate insulation film 5 and the insulating layer 7 to be absorbed by the substrate 1 or the control gate 6. In effect, the exposure of the memory cell transistor to UV light removes the charge from the floating gate 4 into the substrate 1 or into the control gate 6, resulting in the threshold voltage of the memory cell transistor shifted in a negative direction. Characteristic relation between the gate voltage V.sub.G applied to the control gate and the drain current I.sub.D of the MOS memory cell transistor is illustrated in FIG. 2. As shown in FIG. 2, the memory cell transistor has a threshold voltage of about 1 V in the erased state, and of some 6 V in the programmed state. As the reading voltage of the order 5 V is applied to the control gate 6, the erased memory cell transistor conducts, while the programmed memory cell transistor does not conduct. Accordingly, under application of the reading volta V.sub.R of about 5 V to the control gate 6, when the drain current I.sub.D flows in an amount exceeding the sense current Isen, it is determined that the data " 1" is stored in the memory cell. On the other hand, if the flowing drain current I.sub.D is less than the sense current Isen, then it is determined that the data stored in the memory cell is a "0". The sensing of the drain current I.sub.D is performed by a current sensing amplifier provided to the bit line to which the memory cell is connected.
As has been described, the conventional EPROM cell involves a double-gate memory transistor capable of a bi-level data storage in the form of "0" and "1" depending on the electron accumulation on the floating gate.
The conventional non-volatile memory cell of the stacked gate structure, is disadvantageous in that it is limited to the storage of bi-level data or states of "0" and "1", according to the presence and absence of electrons in the floating gate.
If one non-volatile memory cell could store the data of three or more different levels, it instantly leads to an increase in the integration degree of the device and therefore in the memory capacity of the device.